module aru_arb_wrgen (
    input logic                   clk,
    input logic                   rst_n,
          aru_arb_wrgen_cfg_if.in u_aru_cfg_if,
          aru_payload_if.in       u_aru_pld_if,
          arb_wr_req_if.out       u_arb_wr_req_if,
          done_if.out             u_done_if
);

    // Internal interfaces for cfg_pipe
    aru_arb_wrgen_cfg_if u_aru_crd_gen_cfg_if (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_arb_wrgen_cfg_if u_aru_addr_calc_cfg_if (
        .clk  (clk),
        .rst_n(rst_n)
    );

    // Internal interfaces for crd_gen
    aru_idx_if u_aru_idx_if (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_sdb_if u_aru_sdb_if (
        .clk  (clk),
        .rst_n(rst_n)
    );

    // Instantiate cfg_pipe module
    aru_arb_wrgen_cfg_pipe u_cfg_pipe (
        .clk                   (clk),
        .rst_n                 (rst_n),
        .u_aru_cfg_if          (u_aru_cfg_if),
        .u_aru_crd_gen_cfg_if  (u_aru_crd_gen_cfg_if),
        .u_aru_addr_calc_cfg_if(u_aru_addr_calc_cfg_if)
    );

    // Instantiate crd_gen module
    aru_arb_wrgen_crd_gen u_crd_gen (
        .clk         (clk),
        .rst_n       (rst_n),
        .u_aru_cfg_if(u_aru_crd_gen_cfg_if),
        .u_aru_idx_if(u_aru_idx_if),
        .u_aru_sdb_if(u_aru_sdb_if)
    );

    // Instantiate addr_calc module
    aru_arb_wrgen_addr_calc u_addr_calc (
        .clk            (clk),
        .rst_n          (rst_n),
        .u_aru_cfg_if   (u_aru_addr_calc_cfg_if),
        .u_aru_pld_if   (u_aru_pld_if),
        .u_aru_idx_if   (u_aru_idx_if),
        .u_aru_sdb_if   (u_aru_sdb_if),
        .u_arb_wr_req_if(u_arb_wr_req_if),
        .u_done_if      (u_done_if)
    );

endmodule
